1. Field of the Invention
This invention relates to the testing of complex integrated logic networks and more particularly to a simulator oriented fault test generator for testing such complex integrated circuits.
2. Description of the Prior Art
It is well known that high circuit densities and low pin-to-circuit ratios which are characteristic of large scale integrated (LSI) logic design are causing logic modules to be more functional and harder to test. In the prior art a number of test generating techniques have been developed that work well when the input pattern sequence to test a particular fault is short. However, when a long imput pattern sequence is required in order to test for a particular fault, presently known techniques have significant shortcomings. For purposes of brevity, two broad classes of known test generating techniques are described in order to best illustrate that the present invention is a distinctly improved third technique.
A first technique for testing a circuit having inaccessible circuit nodes is by direct analysis. Direct analysis would work very well on the simplified exemplary circuit of FIG. 3, where one skilled in the art could apply the eight potential binary patterns to primary inputs B1, B2, and B3 and by observing the resultant output at primary output B6 draw conclusions about the condition of the network consisting of logic blocks 4 and 5. For a somewhat more complex circuit, this same analysis might be fruitfully performed with the calculations aided by a digital computer. Such a technique becomes increasingly cumbersome as the circuit becomes more complex and includes sequential as well as combinatorial logic circuits. Moreover, such testing is relatively time consuming. Particularly, as the sequential complexity increases, the derivation of binary test pattern sequences to fully test a circuit becomes prohibitively expensive.
In order to alleviate some of the problems associated with the first technique, the second technique of random testing was developed. This random test technique is fully described in the cross reference U.S. Patents to Giedd et al and Carpenter et al. Essentially, in the random technique, a statistically random test pattern (or weighted random test pattern) is applied to the primary inputs of a device under test as well as the primary input of either a "good" or a "simulated good" device. The outputs of these two circuits are compared on a real time basis and if no errors arise within a predetermined time, it may be assumed with some degree of certainty that the logic network under test operates correctly. A problem with random pattern testing is that it is not oriented towards detecting particular faults and thus time might be spent running unnecessary test input patterns. Another problem with random pattern testing is that tests are terminated arbitrarily, rather than after determining that all testable faults are found.